Nvidia and AMD scale AI infrastructure

Two announcements, one bottleneck story

The latest AI-infrastructure news is not only about faster GPUs. On October 12, 2026, AMD introduced Helion, an agentic AI rack blueprint built around open rack-scale infrastructure and AMD compute, while Nvidia and Cisco announced plans for USFP, a pluggable optical-module form factor aimed at 400Gb/s-per-lane Ethernet AI fabrics [1], [4]. Taken together, the announcements frame a market moving beyond single accelerator benchmarks toward the physical realities of deploying large fleets of AI systems: CPU density, rack design, networking bandwidth, power budgets, cooling, serviceability and supplier ecosystems.

AMD’s part of the story is unusually direct. Helion is pitched as an open blueprint for agentic AI infrastructure, not as another pure training rack, and AMD says the design can be configured either as a CPU-only hyperscale rack or as an enterprise rack combining CPU nodes, GPU inference nodes and supporting general-purpose compute [1]. The headline number is 32,768 CPU cores in a CPU-only configuration powered by 6th Gen AMD EPYC processors [1]. That density matters because agentic systems do more than call a model: they plan tasks, execute code, query tools, manage memory, coordinate workflows and handle many concurrent user or enterprise processes.

Why Helion is about CPUs as much as AI

The Helion announcement is a reminder that “AI infrastructure” is not synonymous with “GPU infrastructure.” AMD says the CPU-only Helion rack is designed for hyperscale customers that want dedicated capacity for agent execution while connecting to separate model-inference infrastructure [1]. In practice, that separates two kinds of work: the accelerated model call, and the surrounding compute that decides what to call, when to call it, how to route the request, and what to do with the result.

That distinction is important for agentic AI. A chatbot session may be lightweight from a CPU perspective, but a fleet of autonomous or semi-autonomous agents can look more like a distributed application platform than a single inference job. Each agent may need sandboxed code execution, database access, file handling, retrieval, policy checks, tool calls, scheduling and observability. If thousands of those agents run in parallel, the CPU side becomes a first-class scaling problem rather than a background task.

AMD is also trying to make Helion adaptable. The company says Helion’s OCP spec-based rack blueprint supports open software and liquid- or air-cooled versions, with flexible configurations to match customer needs [1]. Data Center Dynamics reported that AMD expects Helion configurations, now under development with ecosystem partners, to be available in November 2026 and identified partners including Cisco, Dell, Foxconn, HPE, Lenovo, Supermicro and Wiwynn [3]. That partner list matters because AMD is not simply selling a chip story; it is trying to turn CPUs, optional GPUs, racks and OEM/ODM support into a repeatable deployment model.

Tom’s Hardware added a useful implementation detail: Helion is a reference design that AMD is contributing to OCP, with OEMs and ODMs expected to bring systems to market rather than AMD selling complete racks directly [2]. It also reported that AMD revised the availability timing to November 2026, after earlier information pointed to the first half of 2027 [2]. That makes the announcement more immediate, but it also means real-world validation will depend on how partners package the design, how software schedulers allocate work, and whether operators can cool and power dense deployments efficiently.

Nvidia and Cisco attack the network layer

If AMD’s Helion announcement focuses on the compute side of agent execution, Nvidia and Cisco’s USFP announcement focuses on the network bottleneck. The companies said USFP, or Ultra-Dense Small Form Factor Pluggable, is designed for 400Gb/s-per-lane electrical signals and up to 12.8Tb/s of capacity, with the goal of helping AI-factory builders scale Ethernet fabrics without adding network tiers [4]. The companies also claim 4x the bandwidth density and about 1.3x the power efficiency of 200Gb/s-per-lane pluggable optics [4].

The practical problem is familiar to anyone building large AI clusters: accelerators are expensive, and their productivity falls when data movement becomes the constraint. Nvidia and Cisco say that when switch capacity is exhausted, expansion can require additional switch layers and optical links, adding latency, power draw and cost [4]. USFP is meant to keep more bandwidth in a comparable front-panel footprint, allowing more compute systems to be connected within the same network footprint [4].

Cisco’s technical blog frames USFP as a way to preserve what operators already like about pluggable optics: field-replaceable modules, mature supply chains, interoperability, and serviceability [5]. The same blog says the first design path uses 16 lanes at 400Gb/s per lane for 6.4T of aggregate capacity, with a path to 32 lanes and 12.8T [5]. That architecture is not just about raw speed; it is about avoiding operational disruption while the bandwidth requirements of AI fabrics rise.

Open ecosystems are the real battleground

Both announcements lean heavily on openness. AMD says it plans to contribute the Helion specification to OCP for community development and adoption [1]. Nvidia and Cisco say they plan to create an open industry specification for USFP through a community-led multi-source project, while working with TE Connectivity and Amphenol on cages, connectors and modules [4]. In both cases, the strategic message is that no single company can scale AI infrastructure alone.

That openness also reflects a commercial reality. Cloud operators and large enterprises do not want dense, high-power systems that only work in one supplier’s narrow stack unless the performance advantage is overwhelming. They want interchangeable suppliers, familiar service models and a path to future upgrades. Helion’s appeal will depend on whether OEMs and ODMs can turn AMD’s blueprint into reliable, power-efficient systems. USFP’s reach will depend on whether optics suppliers, switch vendors and cloud builders rally around the form factor.

There is a second shared theme: the infrastructure market is becoming more segmented. AMD is explicitly distinguishing between CPU-only hyperscale configurations and all-in-one enterprise configurations [1]. Cisco’s USFP blog similarly argues that AI networking will not be defined by one architecture, noting that pluggable, near-packaged and co-packaged optics each involve different trade-offs [5]. The market is not converging on one universal AI rack or one universal optical answer; it is building a menu of designs for different power, latency, serviceability and deployment constraints.

What to watch next

The key question for Helion is whether 32,768 cores per rack translate into usable throughput. Raw core count is impressive, but agentic workloads can be messy: they involve unpredictable task length, variable memory pressure, external tool latency, security boundaries and complicated scheduling. For hyperscalers, the promise is consolidation and higher density. For enterprises, the promise is a rack that can combine agent execution and inference. In both cases, usable performance will depend on software orchestration as much as silicon.

The key question for USFP is adoption. Nvidia and Cisco have defined an ambitious path for 400Gb/s-per-lane pluggable optics, but the announcement is a plan for a specification and ecosystem, not proof of broad deployment [4]. Investing.com also emphasized that distinction, describing USFP as a specification effort rather than a product launch and noting that adoption will depend on more partners joining the multi-source project [6]. That is the right lens: USFP becomes important only if the ecosystem standardizes around it.

Still, the combined direction is clear. AMD is scaling the CPU-heavy side of agentic AI, where orchestration, code execution and concurrent workflows require dense general-purpose compute. Nvidia and Cisco are scaling the connectivity layer, where high-end accelerators need faster, denser and more power-efficient fabrics. The next wave of AI infrastructure will be judged less by a single chip score and more by how well racks, optics, cooling, power and software work as one system.

Sources from the last 72 hours

1. [1]Introducing AMD Helion, Agentic AI Compute at Rack ScaleOct 12, 2026, 2:00 AM
2. [2]AMD debuts Helion reference design for agentic AI servers with up to 32,768 Zen 6 ‘Venice’ cores — rack design ships later this year in CPU-only and all-in-one configurations [Updated]Oct 12, 2026, 10:01 PM
3. [3]AMD unveils Helion rack to support agentic AI workloadsOct 12, 2026, 2:00 AM
4. [4]NVIDIA and Cisco Introduce New Pluggable Optics Form Factor to Scale AI FactoriesOct 12, 2026, 2:00 AM
5. [5]Cisco and NVIDIA Announce USFP: Expanding the Path to AI ConnectivityOct 12, 2026, 2:00 AM
6. [6]Cisco and Nvidia unveil USFP optical module specification for AI data centersOct 12, 2026, 7:12 PM

AI-generated article based on recent web research, then preserved as a dated editorial snapshot.